The present invention relates generally to a structure and a method of forming a hardened nano-imprinting stamp from silicon carbide. More specifically, the present invention relates to a structure and a method of forming a hardened nano-imprinting stamp using a micro-casting process.
Nano-imprinting lithography is a promising technique for obtaining nano-size (as small as a few tens of nanometers) patterns. A key step in forming the nano-size patterns is to first form an imprinting stamp that includes a pattern that complements the nano-sized patterns that are to be imprinted by the stamp.
In FIG. 1a, a prior nano-imprint lithography process includes an imprinting stamp 200 having a plurality of imprint patterns 202 formed thereon. In FIG. 1b, the imprint patterns 202 consists of a simple line and space pattern having a plurality of lines 204 separate by a plurality of spaces 206 between adjacent lines 204. The imprint patterns 202 are carried by a substrate 211. By pressing (see dashed arrow 201) the imprinting stamp 200 into a specially designed mask layer 203, a thickness of the mask layer 203 is modulated with respect to the imprint patterns 202 (see FIG. 1a) such that the imprint patterns 202 are replicated in the mask layer 203.
Typically, the mask layer 203 is made from a material such as a polymer. For instance, a photoresist material can be used for the mask layer 203. The mask layer 203 is deposited on a supporting substrate 205. Using a step and repeat process, the imprinting stamp 200 is pressed repeatedly onto the mask layer 203 to replicate the imprint patterns 202 in the mask layer 203 and to cover the whole area of the mask layer 203.
In FIG. 2, after the step and repeat process, the mask layer 203 includes a plurality of nano-size impressions 207 that complement the shape of the imprint patterns 202. Next, in FIG. 3, the mask layer 203 is anisotropically etched (i.e. a highly directional etch) to form nano-sized patterns 209 in the mask layer 203. Typically, the supporting substrate 205 or another layer (not shown) positioned between the mask layer 203 and the supporting substrate 205 serves as an etch stop for the anisotropic etch.
In FIG. 4, each line 204 includes opposed side surfaces 204s, a top surface 204t, opposed face surfaces 204f, and edges 204e. A space 206 separates each line 204. Typically, the imprint stamp 200 is made from a material such as silicon (Si). For example, the substrate 211 can be a silicon wafer and the line and space features (204, 206) can be made from silicon (Si) or polysilicon (xcex1-Si). Silicon is the material of choice for nano-imprint stamps because there are well established microelectronics processes for manufacturing silicon based structures and circuits, and because silicon is readily available at a reasonable cost.
However, one of the disadvantages of the prior imprint stamp 200 is that silicon is a soft material and is subject to breakage, damage, and wear from repeated pressing steps into the mask layer 203. In FIG. 4, a section Exe2x80x94E of the line feature 204 is particularly subject to wear, damage, and breakage due to repeated pressing steps. In FIG. 5, an enlarged view of the section Exe2x80x94E of FIG. 4 illustrates that the edges 204e, the top surface 204t, the side surfaces 204s, and the face surfaces 204f are particularly susceptible to wear W from only a few pressing with the mask layer 203.
In FIG. 6, the imprint stamp 200 is pressed 201 into the mask layer 203 so that the line features 204 are disposed in the mask layer 203. Repeated pressing steps cause wear, damage, and breakage denoted as W at the edges 204e and the top surface 204t of the line features 204. Only ten or fewer pressing steps can result in the imprint stamp 200 wearing to the point where it can no longer be used to form consistent, repeatable, and accurate imprint patterns 209.
In FIGS. 7a and 7b,a more detailed view of the wear to the line features 204 shows that the wear is most severe along the edges 204e and top surface 204t as those portions of the line features 204 contact the mask layer 203 first and have surface features that are substantially normal to the direction of pressing 201. Accordingly, as illustrated in FIGS. 8a and 8b, the line feature 204 quickly deteriorates from the ideal line feature 204 of FIG. 8a to the worn out line features 204 of FIG. 8b after only a few pressing cycles with the mask layer 203.
Fabrication of the imprint stamp 200 is one of the most crucial and most expensive steps in the entire imprinting lithography process. Another disadvantage of the prior imprint stamp 200 is that a cost of manufacturing the imprint stamp 200 is not recouped because the imprint stamp 200 is damaged and/or wears out before an adequate number of pressing steps required to justify the manufacturing cost of the imprint stamp 200 can occur. Accordingly, the prior imprint stamp 200 is not economical to manufacture.
Consequently, there exists a need for a nano-size imprinting stamp that is resistant to wear, damage, and breakage. There is also an unmet need for a nano-size imprinting stamp that can retain consistent, repeatable, and accurate imprint patterns over multiple pressing steps so that the cost of manufacturing the nano-size imprinting stamp is recovered.
The micro-casted silicon carbide nano-imprinting stamp of the present invention solves the aforementioned disadvantages and limitations of the prior nano-imprinting stamps. The micro-casted silicon carbide nano-imprinting stamp of the present invention is stronger and tougher because silicon carbide is used as the material for the imprint stamp as opposed to the silicon material of the prior nano-imprinting stamps.
The micro-casted silicon carbide nano-imprinting stamp of the present invention has an increased service lifetime; therefore, the cost of manufacturing the micro-casted silicon carbide nano-imprinting stamp can be recovered because the stamp can withstand many pressing cycles without wearing out, breaking, or being damaged, unlike the prior nano-imprinting stamps that are made from silicon.